Implementing complex image and signal processing algorithms in real time in sometimes low cost hardware may require some algorithm changes. For instance to allow for paralel computation structures. Depending on the implementation floating point calculations may have to be changed by fixed point.
In this project Chess converted and implemented an image processing algorithm requiring several 100 GOPS (Giga operations per second) in complex number floating point in a multiple heterogenous processor architecture consisting of several processing elements implemented in multiple FPGA's connected via Aurora high speed links.
Chess developed and has available specific IP to connect multiple processor elements distributed over multiple FPGA's, discrete pocessors or soft cores (e.g. Xilinx Microblaze). This IP allows for transparent distribution of an algorithm without worring about the underlying processor structure. |
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Parallel Computing Networks)
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